The present invention relates generally to electronic circuits, and more specifically, to a MOS transistor with a forward bulk-biasing circuit.
Recent years have witnessed an increased demand for small, high-performance electronic devices. This demand has been addressed primarily with the evolution of integrated circuits (ICs) designed using very large scale integration (VLSI). Using VLSI, electronic circuits may by designed by combining hundreds of thousands of transistors onto a single IC. This is achieved by miniaturizing transistors to sizes on the order of about 50 nanometer (nm) or less. Integrating large numbers of transistors on a single chip has successfully enabled design of small electronic devices with high processing power.
Although, reduced transistor size leads to a direct design benefit of increased processing power, it also leads to a design trade-off by increasing power consumption of the transistors and hence, that of the ICs. Since the ICs are widely used in portable devices that have limited power storage, it is desirable that the ICs have low power consumption to allow for extended and long-lasting battery life. There are numerous ways in which transistor power consumption can be reduced, for example, by reducing the supply voltage (Vdd) provided to the transistors. However a reduction in the supply voltage Vdd decreases the processing, thereby degrading performance.
Processing speed can be increased by reducing a threshold voltage (Vth) of the transistors. A reduction in threshold voltage Vth can be achieved by forward biasing a bulk terminal of the transistor to increase bulk-to-source (Vbs) voltage. However, a reduction in the threshold voltage Vth of the transistor during power-up and standby modes of the IC leads to an exponential increase in leakage current, which considerably increases leakage power dissipation. Thus, the decreased power consumption obtained by reducing the supply voltage Vdd is nullified by the increased power consumption due to continuous biasing of the bulk terminal during the power-up and standby modes of the IC.
Therefore, it would be advantageous to have a forward bulk-bias circuit that biases a bulk terminal of a transistor of an IC when the IC transitions between power-up and standby modes, improves performance and reduces leakage power dissipation of the transistor, and overcomes the above-mentioned limitations of conventional forward bulk-bias circuits.